The present invention relates to a semiconductor device capable of operating at a high speed with a low power consumption and with which it is possible to further increase the degree of integration of semiconductor integrated circuits, and a method for manufacturing the same.
With the advent of ultra high scale integration of semiconductor integrated circuits, there has been a growing demand in the art for further miniaturization of MIS transistors. A method for manufacturing an MIS transistor having a shallow junction plane is desired for realizing the further miniaturization of MIS transistors.
A conventional method for manufacturing an MIS transistor will now be described with reference to the drawings.
First, referring to FIG. 13A, arsenic (As) ion, which is an N-type impurity, and phosphorus (P) ion, for which the implantation energy and the dose are greater than those for the arsenic ion, are implanted into a semiconductor substrate 101 made of P-type silicon. Then, thermal annealing is performed so as to form an N-type well 101a in an upper portion of the semiconductor substrate 101, and an N-type channel diffusion layer 102 in an upper portion of the N-type well 101a. 
Then, referring to FIG. 13B, a gate oxide film 103 having a thickness of about 2 nm is formed on the semiconductor substrate 101, and a gate electrode 104 made of polycrystalline silicon having a thickness of about 200 nm is formed on the gate oxide film 103.
Then, referring to FIG. 13C, arsenic ion is implanted so as to form a first ion implantation layer 105A, and then boron fluoride (BF2) ion, which is a P-type impurity, is implanted at a lower energy and a higher dose than those for the arsenic ion so as to form a second ion implantation layer. 106A.
Then, referring to FIG. 14A, an insulative film of silicon nitride, or the like, is deposited to a thickness of about 50 nm on the semiconductor substrate 101, and then a side wall 107 is formed from the deposited insulative film by selective etching having a strong anisotropy in a direction perpendicular to the substrate plane.
Then, referring to FIG. 14B, boron fluoride is implanted into the semiconductor substrate 101 using the gate electrode 104 and the side wall 107 as a mask, and then thermal annealing is performed at a high temperature for a short period of time so as to form a P-type extension high concentration diffusion layer 106 from the second ion implantation layer 106A in a region of the semiconductor substrate 101 under the side wall 107, and a pocket diffusion layer 105 from the first ion implantation layer 105A in a region under the P-type extension high concentration diffusion layer 106. At the same time, an N-type high concentration diffusion layer 108 is formed in a region beside the side wall 107.
As described above, boron fluoride (BF2) is used instead of boron (B) for the formation of the P-type extension high concentration diffusion layer 106. It is possible to reduce the effective implantation projected range of boron by the difference in mass between boron and boron fluoride, thereby shallowing the junction of the P-type extension high concentration diffusion layer 106.
With the conventional method for manufacturing an MIS transistor, however, a so-called “dose loss phenomenon” occurs, in which boron atoms forming the P-type extension high concentration diffusion layer 106 are lost through the surface of the semiconductor substrate 101. Due to the dose loss phenomenon, the P-type impurity concentration in the semiconductor substrate 101 after the thermal annealing is reduced, thereby reducing the drivability of the transistor.